Many portable products, such as cell phones, laptop computers, personal data assistants (PDAs) and the like, utilize a processing system that executes programs, such as, communication and multimedia programs. A processing system for such products may include one or more processors, complex memory systems for storing instructions and data, controllers, and peripheral devices configured to interface with the processors and memory over one or more busses. At the same time, portable products have a limited energy source in the form of batteries that are often required to support high performance operations from the processing system. To increase battery life, it is desired to perform these operations as efficiently as possible. Many personal computers are also being developed with efficient designs to operate at reduced energy consumption.
In such processing systems, the processors often achieve performance benefits by allowing memory operations to be performed out of order. For example, a sequence of memory operations may be reordered to allow those operations to the same page in memory to be executed before a new page is opened. Processing systems that are allowed to reorder memory operations are generally referred to as “weakly ordered” processing systems.
In certain instances, the reordering of memory operations may unpredictably affect program behavior. For example, an application may require a first processor to write a block of data beginning at a first memory address and write a data ready flag to a second memory address indicating the block of data is stored. A second processor is to monitor the data ready flag and when the flag indicates the data has been stored, to read the block of data. In a weakly ordered processing system, there is no guarantee that this order of operations will occur, which may be unacceptable. Also, in a weakly ordered processing system, peripheral devices, in addition to the processors, may operate as bus masters for sending data to and receiving data from memory which may further complicate maintaining order of program storage operations.
Various techniques have been employed for executing ordered memory operations in a weakly ordered processing system. One technique is simply to delay certain memory operations until all memory operations before it are executed. In the previous example, the processor may delay issuing a read request until after it writes to the memory location. Another technique is to use a bus command referred to as a barrier command which is issued when an ordered memory operation is required. The barrier command may be used to ensure that all memory access requests issued by a processor before the barrier command are completed before any memory access requests issued by the processor after the barrier command are executed. Again, in the previous example, a barrier command could be issued by the first processor before writing the data ready flag. This barrier command would ensure that the block of data is written to the memory before the data ready flag is written which ensures the second processor reads the newly stored data.
Some processors, peripheral devices, and bus implementations may not recognize barrier commands. Weakly ordered processing systems that utilize barrier commands would be restricted from using such processors, peripheral devices, and busses. As a consequence, the weakly ordered processing systems may not perform efficiently.